CPU

CPU architecture, registers, ALU, control unit, the fetch-decode-execute cycle, pipelining, branch prediction and cache locality, and what they mean for .NET code.

1. What are the main parts of a CPU (cores, registers, ALU, control unit and caches), and how do they work together to run your code?

   A tour of CPU architecture for software engineers: cores and hardware threads, the register file, the ALU and other execution units, the control unit, the cache hierarchy and the clock, and why each matters for .NET performance.

   Junior Theory CPU · 🔗 3 follow-ups
2. Walk through the fetch-decode-execute instruction cycle. How does it apply to the machine code the .NET JIT generates?

   The instruction cycle (fetch, decode, execute, memory access, write-back), the instruction pointer, how jumps, calls and returns change the flow, and how to read a few lines of JIT-generated x64 or Arm64 assembly.

   Junior Theory CPU · 🔗 3 follow-ups
3. What is CPU pipelining, and how do superscalar and out-of-order execution make modern CPUs fast? What stalls a pipeline?

   Instruction pipelining, superscalar issue, out-of-order execution with register renaming and the reorder buffer, the hazards that stall pipelines (data dependencies, branches, cache misses), and how dependency chains show up in .NET code.

   Mid-Level Theory CPU · 🔗 3 follow-ups · 🛠 1 real-world
4. Why can a loop over a sorted array run much faster than the same loop over unsorted data? Explain branch prediction and how to write branch-friendly .NET code.

   How CPUs predict conditional and indirect branches, what a misprediction costs, the classic sorted-versus-unsorted example, branchless techniques, how the .NET JIT uses conditional moves and Dynamic PGO, and how to measure mispredictions.

   Senior Coding CPU · 🔗 2 follow-ups · 🛠 1 real-world
5. What is cache locality? Why is iterating a 2D array row by row much faster than column by column, and how should it influence your choice of .NET data structures?

   Spatial and temporal locality, cache lines and hardware prefetching, row-major layout of C# multidimensional arrays, arrays of structs versus arrays of references, struct-of-arrays layouts, and benchmarking the effects.

   Mid-Level Coding CPU · 🔗 2 follow-ups · 🛠 1 real-world
6. A parallel loop that updates per-thread counters gets slower as you add cores. What is false sharing, how do you detect it, and how do you fix it in .NET?

   Cache coherence and why two threads writing different variables on the same cache line slow each other down, how to recognise and measure false sharing, and fixes: thread-local accumulation, padding, and avoiding shared writes.

   Senior Debugging CPU · 🔗 2 follow-ups · 🛠 1 real-world
7. How do x64 and Arm64 CPU architectures differ, and what does a .NET team need to check before running services on Arm64 servers or developing on Apple Silicon?

   CISC versus RISC design, instruction sets, memory ordering models and SIMD differences between x64 and Arm64, and the practical checklist for .NET: RIDs, native dependencies, multi-arch container images, concurrency correctness, performance testing and cost.

   Mid-Level Theory CPU · 🔗 3 follow-ups · 🛠 1 real-world
8. What is SIMD, how do CPU vector registers work, and when would you use Vector128<T>, Vector256<T> or Vector<T> in .NET?

   Single instruction, multiple data: vector registers and instruction sets (SSE, AVX2, AVX-512, NEON), the .NET hardware-intrinsic APIs, vectorised BCL methods and TensorPrimitives, writing a vectorised loop with a scalar tail, and when SIMD is or isn't worth it.

   Senior Coding CPU · 🔗 2 follow-ups · 🛠 1 real-world